From a technology presentation held at CERN in Geneva last January 29, it has emerged as unofficial direct information on the next generation of AMD Opteron processor-based architecture Zen.
We know how the return hopes of AMD in the market of processors for higher performance, and especially with reference to the datacenter, have been returned to its architectural peculiarities in Zen. What the company has so far said it is an increase in computing power in terms of instructions per clock cycle of 40% compared to the current generation of AMD Opteron processors.
The presentation of CERN confirmation information already issued previously, and in part deductible knowing the architecture of the processors for high-power computing systems. The CPU Opteron versions with 32 physical cores, combined with symmetrical multi threading for a maximum of 64 threads processable in parallel, will be obtained through the union of two die to 16 cores each.
It is a MCM design, multi-chip module, which facilitates the construction of versions of processor characterized by a high number of cores without having to necessarily provide for the construction of a specific die which integrates them all in-house.
The use of an MCM design also will allow to have a DDR4 memory controllers particularly sophisticated, equipped with 8 channels. Each day of Zen Opteron processor will contain an internal controller DDR4 type quad channel and up to 16 cores; the union of two die with MCM design so will double the cores and up to 8 channels to expand the width of the memory controller.
Before seeing all this work will then have to wait another several months: AMD provides for the launch of the FX family CPU architecture-based Zen by the end of 2016, with the launch of the Opteron proposals in early 2017 and then in about one year.
We know how the return hopes of AMD in the market of processors for higher performance, and especially with reference to the datacenter, have been returned to its architectural peculiarities in Zen. What the company has so far said it is an increase in computing power in terms of instructions per clock cycle of 40% compared to the current generation of AMD Opteron processors.
The presentation of CERN confirmation information already issued previously, and in part deductible knowing the architecture of the processors for high-power computing systems. The CPU Opteron versions with 32 physical cores, combined with symmetrical multi threading for a maximum of 64 threads processable in parallel, will be obtained through the union of two die to 16 cores each.
It is a MCM design, multi-chip module, which facilitates the construction of versions of processor characterized by a high number of cores without having to necessarily provide for the construction of a specific die which integrates them all in-house.
The use of an MCM design also will allow to have a DDR4 memory controllers particularly sophisticated, equipped with 8 channels. Each day of Zen Opteron processor will contain an internal controller DDR4 type quad channel and up to 16 cores; the union of two die with MCM design so will double the cores and up to 8 channels to expand the width of the memory controller.
Before seeing all this work will then have to wait another several months: AMD provides for the launch of the FX family CPU architecture-based Zen by the end of 2016, with the launch of the Opteron proposals in early 2017 and then in about one year.
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